The Tenstorrent team combines technologists from different disciplines who come together with a shared passion for AI and a deep desire to build great products. We value collaboration, curiosity, and a commitment to solving hard problems.
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SOC Fabric Architect
Software 2.0 is redefining the computing paradigm. The new paradigm computation demand is incommensurable with the existing software and hardware criteria. The solutions require unifying the innovations on the software programming model, compiler technology, heterogenous computation platform, networking technology, and semiconductor process and packaging technology. Do you want to join a dynamic team of hardware and software architects building the leading hardware platform for Machine Learning and Artificial Intelligence?
- Collaborate with the software team and platform architecture team to understand fabric bandwidth and latency requirements and real-time constraints for AI accelerator, CPU, security, and networking traffic. Devise QoS and ordering rules among the CPU, accelerator, and IO coherent/non-coherent traffics.
- Identify representative traffic patterns for the software applications. Perform data-driven analysis to evaluate fabric topology, QoS, memory architecture, and u-architecture solutions to improve performance, power efficiency, or reduce hardware.
- Create directory-based cache coherency specification to satisfy performance requirements of coherent multiple-cluster CPU system and accelerator. Make tradeoff protocol complexity and performance requirements.
- Set SOC fabric architecture direction based on the data analysis and work with a cross-functional team to achieve the best hardware/software solutions to meet PPA goals.
- Develop an SoC cycle-accurate performance model that includes memory sub-systems, directory-based coherent cache controllers, fabric interconnects, and fabric switches that describe the microarchitecture and use it to evaluate new features.
- Collaborate with RTL and Physical design engineers to make power, performance, and area tradeoffs.
- Drive analysis and correlation of performance feature both pre and post-silicon.
Experience and qualifications:
- BS/MS/PhD in EE/ECE/CE/CS
- Strong grasp of NoC topologies, routing algorithms, QoS, and
- Expertise in cache coherency protocols (AMBA CHI/AXI protocol), DDR/LPDDR/GDDR memory technology, and IO technology (PCIe/CCIX/CXL).
- Prior experience or a strong understanding of traffic patterns for ML/AI algorithms in a heterogeneous computation system is a plus.
- Prior experience on formal verification of cache coherency protocol is a plus.
- Proficient in C/C++ programming. Experience in the development of highly efficient C/C++ CPU models.
Multiple geographies: Austin, Santa Clara, Toronto, Seattle